The following signals are available for extra IO ports:
Signal
Where
Level
A0
?
3.3V
R/W
?
3.3V
CS2
?
3.3V
CS3
?
3.3V
IRQ_PC?
?
3.3V
IRQ_PC?
?
3.3V
Signal
Where
Level
D0
?
5V
D1
?
5V
D2
?
5V
D3
?
5V
D4
?
5V
D5
?
5V
D6
?
5V
D7
?
5V
UBOOT maps CS2 to a 64K range at 0xfxxx0000, CS3 is mapped to a 64K range at
0xfyyy000.
Schematic for 2 8-bits output and 2 8-bits input ports:
Vcc is 5V for all logic chips.
The 3.3V signals from the processor are converted to 5V signals by a 74HCT244.
Both signals to PortC are levelshifted with resistors.
The level shifters for the databus are already on the original CC1000.
Only CS2 is used.
Duplicating this circuit, using CS3 and the second part of the '139 adds 4 more
ports.
If one of the output ports is used as an 8 bits address bus,
an addressable IO space of 256 bytes is created.
Archive containing the hardware related
Xcircuit files.
![[cc1000_ioports.png]](cc1000_ioports.png)